Accuracy-Configurable Floating-Point Multiplier Design for SRAM-Based Compute-in-Memory | Yiqi Zhou et al. | ResearchPod

Transcript: Accuracy-Configurable Floating-Point Multiplier Design for SRAM-Based Compute-in-Memory

Alex: Welcome to another episode of ResearchPod. Today, we're looking at a new way to help AI devices run complex calculations without draining their batteries. Sam, what's the core challenge this paper is trying to solve?

Sam: The problem is something engineers call the "memory wall." In modern AI devices—like a smart camera or a wearable sensor—the processor has to constantly shuttle data back and forth from memory just to do its calculations. That back-and-forth uses up a surprising amount of power. This research focuses on a solution called Digital Compute-in-Memory, or DCiM. The idea is to perform those calculations directly inside the memory itself, rather than moving the data somewhere else to process it. But there's a catch: most of these systems are currently limited to simple, whole-number math, and they struggle with the more precise calculations that modern AI models actually require.

Alex: So the paper is asking how we bring that higher-precision math into memory-based systems without making the hardware too large or power-hungry?

Sam: Exactly. The researchers want to make high-precision math as cheap and efficient as the simpler math these systems already handle well. If they can pull that off, it opens the door to running sophisticated AI models directly on small, battery-powered sensors.

Alex: Why is high-precision math so much harder for these systems in the first place?

Sam: Think of it like the difference between counting whole apples and measuring the precise weight of a chemical compound. Computers represent very large or very small numbers with high precision using a format called floating-point—following a standard rulebook called IEEE 754. Because these numbers have to track both the significant digits and the scale of the number simultaneously, the hardware needed to multiply them is far more complex. It takes up significantly more physical space on a chip.

Alex: So it's like trying to fit a large, complicated calculator into a very cramped space. If you add that calculator to every single memory cell, you run out of room quickly.

Sam: Precisely. And that's where the authors introduce their central technique, which they call Mantissa Segmentation. To understand it, think about a large financial transaction. You need to get the dollar amount exactly right, but a small rounding difference in the cents won't meaningfully change the outcome.

Alex: So they're splitting the number into the part that really matters and the part that matters less—and only doing the expensive, precise calculation on the important part?

Sam: That's the core idea. In floating-point numbers, the "mantissa" is the portion that holds the significant digits—the meaningful part of the value. The researchers split this mantissa into two segments: a high-significance portion and a low-significance portion. They calculate the high-significance part exactly, because that's where most of the value lies. For the low-significance part, they use an approximation—or sometimes skip the calculation entirely—to save on hardware.

Accuracy-Configurable Floating-Point Multiplier Design for SRAM-Based Compute-in-Memory

Yiqi Zhou, Junhao Lu, Jiale Yu, Zhuo Xu, Yang He, Yue Yuan, Shan Shen, Daying Sun

Jun 7, 2026·5:20·arxiv·Original Paper

Compute-in-Memory (CiM)Approximate ComputingFloating-Point MultiplierMantissa SegmentationOpenACM

Listen

5 min

Summary

Research Question

As edge AI demands grow, SRAM-based Compute-in-Memory (DCiM) has become a popular solution to overcome the von Neumann bottleneck. However, most existing DCiM frameworks are limited to integer or fixed-point arithmetic. While floating-point support is desirable for neural network inference, integrating standard IEEE 754 floating-point units into dense memory arrays is prohibitively expensive in terms of area and power. This paper addresses this gap by integrating accuracy-configurable floating-point multipliers into the OpenACM framework.

Approach

The researchers implement an exact IEEE 754-compliant multiplier as a baseline and propose an approximate floating-point multiplier (AFPM) based on mantissa segmentation. The mantissa is divided into high-significance and low-significance segments. The high-significance segment is computed exactly, while the low-significance segments are conditionally executed or omitted to save hardware resources. The design includes a lightweight shift-based compensation mechanism to mitigate the numerical error introduced by these approximations. This multiplier is fully integrated into the OpenACM compiler flow, allowing designers to treat floating-point precision as a configurable optimization knob.

Main Findings

Post-layout results demonstrate that the proposed approximate multipliers significantly outperform exact IEEE 754 designs. Specifically, the approximate configurations achieve up to 69% reduction in logic area and 72% power savings. Because the critical path in these SRAM-based systems is dominated by memory access rather than the multiplier logic, these savings are achieved without increasing the overall system delay. Evaluations on image processing tasks and ResNet-18 inference show that these hardware optimizations result in negligible accuracy degradation, validating the approach for practical edge AI applications.

Why It Matters

This work bridges the gap between arithmetic-level approximate computing and system-level DCiM compilation. By exposing floating-point precision as a compiler-integrated parameter, the authors enable systematic hardware-software co-optimization. This flexibility is critical for deploying energy-efficient, high-performance AI models on resource-constrained edge devices where area and power budgets are extremely tight.

Key Terms and Definitions

Compute-in-Memory (CiM) — An architecture that performs arithmetic operations directly within memory arrays to minimize energy-intensive data movement.
Mantissa Segmentation — A technique that divides the mantissa of a floating-point number into segments of varying significance to allow for selective, approximate computation.
OpenACM — An open-source, accuracy-aware compilation framework for SRAM-based approximate DCiM architectures.
IEEE 754 — The standard technical specification for floating-point arithmetic, defining formats and rounding behaviors for computer systems.
Hidden Bit — The implicit leading bit (typically 1) in a normalized floating-point significand that is not stored in memory but is restored during hardware processing.

Abstract

Digital Compute-in-Memory (DCiM) reduces data movement and has become a promising solution for energy-efficient edge AI. However, most existing DCiM frameworks still primarily target integer or fixed-point arithmetic, and provide limited support for compiler-integrated and accuracy-configurable floating-point computation. Directly integrating conventional IEEE 754 floating-point units into dense SRAM-based DCiM arrays, however, incurs high area and power overhead. To address this challenge, this work presents an accuracy-configurable floating-point multiplier integrated into the OpenACM framework for SRAM-based DCiM. An exact IEEE~754-compliant multiplier is first implemented as a baseline, and a mantissa-segmentation-based approximate multiplier is then proposed to reduce hardware cost while preserving numerical fidelity. Post-layout results show up to 69% logic area reduction and 72% power savings over exact floating-point designs without delay overhead. Evaluations on image processing tasks and ResNet-18 inference further demonstrate negligible accuracy degradation. These results indicate that compiler-integrated approximate floating-point multiplication is a practical approach for enabling efficient and configurable floating-point support in SRAM-based DCiM systems. The Floating-Point Multiplier is available on https://github.com/ShenShan123/OpenACM

Accuracy-Configurable Floating-Point Multiplier Design for SRAM-Based Compute-in-Memory: Research Paper Podcast