Revisiting Thermal Scalability for Large-Scale Superconducting Quantum Systems

Scaling superconducting quantum systems to the thousands of physical qubits required for fault-tolerant quantum computing (FTQC) is fundamentally constrained by cryogenic infrastructure. While previous thermal models focused on passive heat conduction through control lines and attenuator dissipation, these models often overlooked the heat generated by the readout amplification chain. As modern systems adopt lower-heat cabling and higher-capacity refrigerators, the thermal landscape has shifted, making the 4 K stage—where readout amplifiers are typically located—the primary bottleneck.

This study introduces a comprehensive, system-level thermal estimation framework that integrates active, passive, and ohmic heat loads. Unlike prior models, this framework explicitly accounts for the heat footprint of cryogenic amplifiers (such as HEMTs) and their associated bias wiring. The authors also integrate a logical-error analysis, allowing researchers to map physical qubit (PQ) capacity directly to logical qubit (LQ) yield, providing a more relevant metric for assessing the utility of a quantum system.

The authors show that omitting amplifier-related heat leads to significant overestimation of system scalability and misidentification of the limiting temperature stage. By re-evaluating prior studies, they demonstrate that as cabling technologies improve (e.g., moving from stainless steel to modern microstrip interconnects), the thermal bottleneck migrates from the millikelvin stages to the 4 K stage. The study further explores the design space of amplifier and wiring combinations, revealing that reducing active dissipation alone is insufficient if it leads to increased passive or ohmic heat loads in the bias lines. These insights are used to evaluate pathways toward 10k-qubit systems, highlighting the necessity of balancing component-level thermal performance with system-level constraints.