Sampling hard circuits with verifiably high fidelity

As quantum processors scale, demonstrating a clear quantum advantage requires balancing three competing goals: maintaining classical hardness, suppressing hardware noise, and verifying the fidelity of the computation. Existing methods often struggle to satisfy all three, as hardware-friendly circuits are difficult to protect with error-correcting codes, while highly structured, verifiable circuits are often easier to simulate classically.

The authors propose Doped Clifford Sampling (DCS), which utilizes a Clifford circuit as a high-entanglement backbone. This backbone is encoded in a spacetime code, which allows for the measurement of code syndromes to detect and reject errors. To achieve classical hardness, the authors "dope" the Clifford circuit with T gates. Because these T gates are placed in locations that commute with the code's stabilizers, they do not interfere with the error-detection mechanism. This allows the researchers to use the fidelity of the Clifford circuit as a proxy to lower-bound the fidelity of the more complex, classically hard doped circuit.

The team implemented this protocol on a 70-qubit superconducting processor using 97 physical qubits. By post-selecting on zero-syndrome measurements, they suppressed gate error rates by a factor of 10. The resulting doped circuit, containing 468 T gates, achieved a fidelity lower bound of 0.284 with 95% confidence. The authors validated this bound by performing direct fidelity estimation (DFE) on circuits with lower doping counts and by showing that syndrome distributions remained consistent across different doping levels, confirming that the T gates did not introduce significant new noise.