Taming Spacetime Overhead and Design Complexity in Distributed Fault-Tolerant Superconducting Quantum Computation

Scaling fault-tolerant superconducting quantum computers to utility-scale sizes—such as those required to factor RSA-2048 or simulate complex quantum chemistry—demands millions of physical qubits, far beyond the capacity of a single monolithic quantum processing unit (QPU). This paper investigates whether distributed fault-tolerant quantum computation (DFTQC) architectures, built by networking multiple smaller manufacturable chips via quantum interconnects, can achieve scalability without prohibitive spacetime overhead or heavy system orchestration burdens.

The authors develop a hardware-grounded architectural co-design together with a comprehensive resource-estimation protocol tailored for surface-code-based modular processors. By confining inter-chip latency and noise strictly to module boundaries, the design prevents slow, noisy remote links from turning into global performance bottlenecks. Using RSA-2048 factorization as a demanding benchmark, the study evaluates physical resource costs under experimentally anchored parameters and realistic superconducting hardware constraints.

The co-designed distributed architecture requires only modest additional resource overhead compared to a large, ideal monolithic baseline. For a physical two-qubit gate error rate of 10^-3 in the bulk, with inter-chip operations being ten times noisier and up to twenty-five times slower, factoring RSA-2048 requires approximately 2.0 million physical qubits and an expected runtime of 4.4 days. In comparison, a monolithic baseline using identical QEC strategies requires about 1.3 million physical qubits and 3.4 days. This translates to an increase in the surface-code distance from d = 27 to d = 31, representing roughly a 60% increase in physical qubits and a 30% increase in execution time.

Crucially, this additional overhead is nearly scale-invariant across a wide module-capacity window ranging from thousands to nearly two hundred thousand physical qubits per chip. Because inter-chip noise and latency are localized boundary costs, chip size is decoupled from global performance. This turns module capacity from a finely tuned architectural parameter into a flexible engineering degree of freedom governed primarily by chip manufacturability, wiring, and packaging constraints.