ResearchPod Summary
Neutral Atom Quantum Computing (NAQC) relies on the precise arrangement of atoms into defect-free arrays. This process requires repeated fluorescence imaging and physical rearrangement of atoms using optical tweezers. In conventional setups, these tasks are managed by a host computer, which introduces significant round-trip latency when communicating with the FPGA-based control hardware. This bottleneck is particularly problematic for quantum error correction (QEC) and mid-circuit feedback, where rapid, low-latency control is essential for maintaining coherence.
AtomFlow addresses this by consolidating the entire initialization and readout pipeline onto a single Zynq UltraScale+ FPGA. By co-locating the image processing module—which reconstructs atom occupancy from noisy fluorescence data—with a newly developed atom-rearrangement engine, the system removes the need for host-to-backend data transfers. The architecture utilizes a streaming interface that emits rearrangement moves as soon as they are computed, allowing the system to interleave move generation with physical execution.
Implemented using High-Level Synthesis (HLS), AtomFlow features a parallel by-row lattice sorting algorithm. The design is modular, allowing for easy switching between initialization (rearrangement) and readout (state measurement) modes. On a 16x16 atom array, the system achieves a first-move latency of 4 ms and an average move generation rate of 1 ms. This performance ensures that the control logic can keep pace with the physical movement of atoms, effectively hiding the computational overhead of the rearrangement algorithm.
By moving the control logic from software to hardware, AtomFlow provides a scalable path toward larger quantum processors. The ability to perform mid-circuit feedback and rapid array initialization without host intervention is a critical step toward practical, high-fidelity quantum computing, especially as the number of qubits scales into the thousands.
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