SpiderLS: Leveraging Full ZX Reduction for Lattice Surgery Compilation

As quantum programs scale, translating logical circuits into efficient lattice surgery realizations is critical for minimizing spacetime costs. Existing compilers often restrict ZX-calculus reductions to preserve specific diagram structures that map directly to bounded-degree lattice surgery junctions. This paper asks whether leveraging full ZX reduction—which can produce higher-arity interactions—can further optimize lattice surgery compilation without sacrificing scalability.

SpiderLS introduces a compilation pipeline that treats ZX-diagrams as a flexible intermediate representation. Unlike prior work that limits ZX reduction to maintain a one-to-one correspondence between spiders and four-port junctions, SpiderLS performs full ZX reduction. It recognizes that higher-arity interactions can be realized through multi-patch measurements. The compiler derives an execution order from the reduced graph, groups compatible interactions into multi-target operations, and lowers them to Pauli-product measurements (PPMs). Finally, it employs a structure-aware, layered spacetime routing strategy that performs bounded local searches to place and route logical patches, avoiding the high computational overhead of global search-based embedding.

SpiderLS consistently outperforms state-of-the-art lattice surgery compilers. Across a diverse suite of algorithmic and random workloads, it achieves an average reduction of 49.2% in spacetime volume and 99.8% in compilation time compared to the previous ZX-based compiler, TopoLS. The framework demonstrates strong scalability, maintaining efficient performance as circuit width increases, and shows that temporal compression via multi-patch measurements does not lead to an unmanageable concentration of magic state demand.

This work demonstrates that the constraints traditionally imposed on ZX-diagrams for lattice surgery are overly restrictive. By decoupling the ZX-level representation from the physical junction-based model, SpiderLS enables more aggressive circuit optimization. The results suggest that compilers can achieve significant resource savings by embracing the full expressiveness of ZX-calculus and using structure-aware routing to bridge the gap between logical diagrams and physical spacetime realizations.