Latency-Constrained Hardware-Aware Quantum Error Correction Co-Design with Adaptive Confidence-Gated Neural Decoding for the Rotated Surface Code

This paper investigates how to overcome the real-time decoding bottleneck in scaling quantum error correction (QEC) for fault-tolerant quantum computing. Traditional decoders like minimum-weight perfect matching (MWPM) are computationally expensive, while purely neural network decoders struggle with the rare, hard syndromes that dominate logical error rates. To solve this, the author introduces an adaptive confidence-gated decoding framework that treats decoding as a two-stage inference problem.

A lightweight feed-forward neural network acts as a fast-path decoder for the vast majority of syndrome measurements, simultaneously outputting a correction and a calibrated confidence score. When the confidence falls below a tunable threshold, the syndrome is escalated to an MWPM refinement stage. The framework is systematically evaluated on rotated surface codes with distances $d in \{3, 5, 7, 9, 11\}$ under circuit-level depolarising noise using the Stim simulator.

By routing only a small fraction (3.3% to 6.2%) of syndromes to the refinement stage at a confidence threshold of 0.95, logical accuracy improves significantly compared to a neural-only baseline. Furthermore, neural-decoder throughput saturates near $4.6 \times 10^5$ samples per second at batch size 512 on commodity CPU hardware. This indicates that the neural fast path ceases to be the dominant throughput bottleneck beyond code distance $d = 7$, proving the feasibility of hybrid control stacks.

As physical qubit counts scale up, the classical control stack must process syndrome measurements within strict hardware coherence constraints. This study bridges the gap between fast neural inference and the high accuracy of graph-based matchers, offering a concrete architectural module for latency-constrained hardware-aware quantum error correction co-design.