Design of a Quantum Error Correction Decoder Exploiting Temporal Parallelism

As quantum processors scale, the time required to decode error syndromes must remain within the microsecond-scale syndrome measurement cycle to prevent exponential error accumulation. While theoretical methods like sandwich decoding offer a way to parallelize this process, there has been a lack of concrete microarchitectural designs and quantitative evaluations of their performance on actual hardware. This paper addresses this gap by proposing and implementing an ASIC-based sandwich decoder using the Union-Find algorithm.

The authors propose a parallel-processing microarchitecture that implements sandwich decoding—a method that decomposes the three-dimensional spatiotemporal decoding graph into smaller, overlapping windows. By using two types of decoders, the system can process these windows in parallel. The design includes a Window Dispatcher to manage streaming syndrome data via a ring buffer and a Seam Pairer to coordinate the reconciliation of error chains across window boundaries. The core logic utilizes the Union-Find algorithm, optimized for hardware implementation, to estimate error locations efficiently.

The proposed decoder was implemented in SystemVerilog and evaluated through logic synthesis and simulation. At a code distance of d=21, the sandwich decoder achieved an average latency reduction of 35% and a worst-case latency reduction of 12% compared to a standard batch Union-Find decoder. Crucially, the system maintains a logical error threshold of approximately 1.5% under phenomenological noise, demonstrating that the speedup does not come at the cost of significant accuracy degradation. The design successfully addresses the challenges of asynchronous data processing and inter-window dependency management required for high-speed, continuous quantum error correction.