ZeroG: A Pre-Decoder-Aware Decoder for Quantum Error Correction

As quantum error correction (QEC) scales, the classical decoder often becomes the bottleneck, creating an exponential backlog of syndromes that stalls computation. While hierarchical decoding—using a pre-decoder to resolve simple errors before passing a sparse residual to a strong decoder—is a promising strategy, existing strong decoders are designed for dense syndromes and fail to exploit the sparsity provided by pre-decoders. This paper asks: can we design a strong decoder that is explicitly aware of pre-decoding to reduce latency while maintaining high accuracy?

The authors introduce ZeroG, a strong decoder co-designed with pre-decoders. Unlike traditional decoders that treat the input as a dense graph, ZeroG uses a stochastic approximate minimum-weight perfect matching (MWPM) algorithm that focuses on the sparse residual syndromes. The system architecture decouples the control plane (ZeroG Manager) from the data plane (ZeroG Decoding Core). This separation allows the same algorithmic specification to be deployed across heterogeneous hardware, including both CPU thread pools and FPGA fabric, without requiring separate implementations.

ZeroG demonstrates a 10x latency improvement over state-of-the-art strong decoders while matching their logical error rates. It achieves worst-case decoding times of under 350ns for code distances up to d=15. Furthermore, the architecture is highly scalable, supporting up to 640 logical qubits on a single 128-core CPU and 32 logical qubits on a single AMD Versal V80 FPGA. By allowing users to dynamically trade latency for accuracy, ZeroG provides a flexible solution that fits within the strict timing budgets required for superconducting quantum architectures.