Real-time decoding of quantum error correction codes using high-performance computing

As quantum processors scale, the classical hardware responsible for quantum error correction (QEC) must process syndrome measurements and return corrective actions within a microsecond-scale window to prevent data backlogs. This paper addresses the challenge of building a scalable, low-latency, and programmable decoding architecture that bridges the gap between quantum processing units (QPUs) and high-performance computing (HPC) clusters.

The authors propose THQLink, an architecture that utilizes the TH-Express high-speed interconnect to link FPGA-based quantum controllers with general-purpose HPC nodes. Unlike standard Ethernet or PCIe-based solutions, TH-Express is designed to minimize protocol overhead and provide deterministic, low-latency communication. The system employs a parallel window decoding strategy, which partitions syndrome data into overlapping temporal windows. This allows multiple compute nodes to process decoding tasks concurrently, effectively overlapping syndrome acquisition with the computation of error corrections.

THQLink achieves an average round-trip latency of 2.944 microseconds, representing a 23.3% improvement over existing architectures like NVQLink. The system demonstrates high scalability, with an incremental latency overhead of only 130 nanoseconds per additional network hop. Using this framework, the researchers successfully implemented a closed-loop decoding pipeline for surface codes up to distance 19, maintaining a real-time decoding rate of 1 microsecond per QEC round on standard CPUs. This confirms that general-purpose HPC resources, when properly integrated, can meet the stringent timing requirements of fault-tolerant quantum computing while offering greater flexibility than fixed-function ASIC or FPGA-only decoders.